Manufacturers of routing platforms, such as the assignee of the present application, are designing new routing platforms that will be orders of magnitude faster than existing products. These routing platforms will require high-capacity external memory chips for storing packets that are faster than any memory products now available or being designed.
A routing processor includes switching engines, such as Application Specific Integrated Circuits (ASICs), that receive packets at a very high rate and must quickly store the packets in an external high-capacity, high-speed memory. The ASIC then determines the route of the packet and accesses the packets from memory at a very high rate to be forwarded to the next destination. This is the store and forward memory model.
The fastest external memory integrated circuits (ICs) now in existence are SRAMs utilized as caches in workstations. The workstation needs access to data almost instantaneously and therefore the latency of the cache, i.e., the time delay between requesting and receiving data from the memory, is very low.
Currently, as technology allows for faster chip designs, SRAM manufacturer's are increasing the size of the memory chips. As is known in the art, as chip size increases the time to retrieve data from a chip increases. Therefore, current projections for SRAM speeds predict manufacturers will elect to increase chip size thereby not significantly increasing throughput.
Small, embedded, high-speed internal RAMs coupled to logic inside ASICs and other custom chips currently exist that operate at speeds up to 500 to 700 MHz. These small arrays can be made to run very fast by limiting the number of cells on each word line and bit line. Such techniques are commonly used in 1st level cache integrated with CPUs that today run up to multiple GHz.
However, these embedded, high-speed RAMs cannot be directly connected to function as external RAM for the types of ASICs used in routing platforms and do not have enough capacity to serve as packet storage memories for switching ASICs.